pigeon-labs-stack/v100-sxm2-reference

Claims below include README evidence. A matching quote or worker agreement does not establish that a claim is correct. Category majority among 2 workers. Version 1.

A public reference kit with pin maps, NVLink connection plans and KiCad connector resources for carrier boards built around NVIDIA V100 SXM2 modules.

This project aims to become an **open-source carrier-board design for NVIDIA V100 SXM2 modules**

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

It shares pin mappings, connection plans and connector-only KiCad files so other people can develop their own designs while the full carrier board is developed.

this reference kit shares the pin mappings, connection plans and connector-only KiCad resources so other people can develop their own designs.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

The work is mainly curation: public information gathered, sources compared, and connector orientation and signal names reconciled into clearer references.

gathering public information, comparing sources, reconciling connector orientation and signal names, and making the results easier to follow.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

800 canonical contacts, 400 on connector A and 400 on connector B, with signal names, evidence and electrical notes.

**800 canonical contacts:** 400 on connector A and 400 on connector B, with signal names, evidence and electrical-treatment notes.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Two- and four-GPU connection tables with exact connector B pads, directions, lanes and polarity.

**Two- and four-GPU connection tables:** exact Connector B pads, directions, lanes and polarity.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Three editable KiCad starters: one module, plus two- and four-module versions with NVLink data connected.

**Three editable KiCad starters:** one module’s A/B connectors, plus two- and four-module versions with NVLink data connected.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Each V100 needs a 156.25 MHz differential NVHS clock on B/E20 (+) and B/F20 (-).

Each V100 needs a **156.25 MHz differential NVHS clock on B/E20 (+) and B/F20 (−)**.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

The separate PCIe clock is 100 MHz on A/E7 (+) and A/F7 (-).

The separate PCIe clock is **100 MHz on A/E7 (+) and A/F7 (−)**.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Includes a standalone dark reference workbook.

the standalone dark reference workbook

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Complete schematic PDFs can be read without KiCad.

use the [complete schematic PDFs](docs/downloads.md#read-without-kicad)

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Provides 800 canonical contacts with signal names, evidence, and electrical-treatment notes for connectors A and B.

800 canonical contacts: 400 on connector A and 400 on connector B, with signal names, evidence and electrical-treatment notes

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Includes connection tables for two- and four-GPU configurations detailing pads, directions, lanes, and polarity.

Two- and four-GPU connection tables: exact Connector B pads, directions, lanes and polarity

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Offers three editable KiCad starters for single, two, and four-module configurations with NVLink data connected.

Three editable KiCad starters: one module’s A/B connectors, plus two- and four-module versions with NVLink data connected

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Features Catppuccin Mocha visuals including contact maps, topology diagrams, and a standalone dark reference workbook.

Catppuccin Mocha visuals: contact maps, topology diagrams, schematic previews and the standalone dark reference workbook

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Specifies the requirement for a 156.25 MHz differential NVHS clock on specific pins for NVLink operation.

Each V100 needs a 156.25 MHz differential NVHS clock on B/E20 (+) and B/F20 (−)

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Documents the separate PCIe clock requirement of 100 MHz on designated pins.

The separate PCIe clock is 100 MHz on A/E7 (+) and A/F7 (−)

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Derives the two-GPU arrangement from documented pairing families and the four-GPU arrangement from curated topology.

The full six-group two-GPU arrangement is derived from the documented pairing families; the four-GPU arrangement follows the curated topology

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Includes a local reference footprint with 800 contact pads, housing outlines, and mounting features.

The actual local reference footprint, exported directly by KiCad: 800 contact pads, housing outlines and mounting features

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: This is a public reference pre-release, not a hardware-qualified carrier board.

This is a public reference pre-release, not a hardware-qualified carrier board.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The KiCad starters include no regulator, power-control or clock circuits.

No regulator, power-control or clock circuits are included.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: A raw PCB footprint is not included in this edition.

A raw PCB footprint is not included in this edition

Quote matched the README or GitHub description at extraction. Same claim and quote from 2 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The NVLink plans are logical connection plans, not routed bridge schematics.

These are logical connection plans, not routed bridge schematics.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The NVLink starters show data wiring, not a complete working NVLink implementation.

the NVLink starter schematics show data wiring, not a complete working NVLink implementation

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: Routed boards, manufacturing outputs and hardware qualification are future work.

Routed boards, manufacturing outputs and hardware qualification are future work.

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The project is a public reference pre-release and not a hardware-qualified carrier board.

This is a public reference pre-release, not a hardware-qualified carrier board

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The KiCad starters do not include regulator, power-control, or clock circuits.

No regulator, power-control or clock circuits are included

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: The NVLink schematics show data wiring but are not a complete working NVLink implementation.

The NVLink starter schematics show data wiring, not a complete working NVLink implementation

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

Limitation: Routed boards, manufacturing outputs, and hardware qualification are future work.

Routed boards, manufacturing outputs and hardware qualification are future work

Quote matched the README or GitHub description at extraction. Same claim and quote from 1 worker(s). Interpretation not reviewed by a maintainer.

embedded